create_clock -name input_clk -period 40 -waveform {0 20} [get_ports {input_clk}]
derive_pll_clocks
rename_clock -name {sys_clk} -source [get_ports {input_clk}] -master_clock {input_clk} [get_pins {u_pll/pll_inst.clkc[0]}]
rename_clock -name {uart_clk} -source [get_ports {input_clk}] -master_clock {input_clk} [get_pins {u_pll/pll_inst.clkc[1]}]
